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GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
COCO
2009
Springer
128views Algorithms» more  COCO 2009»
16 years 1 months ago
An Almost Optimal Rank Bound for Depth-3 Identities
—We show that the rank of a depth-3 circuit (over any field) that is simple, minimal and zero is at most O(k3 log d). The previous best rank bound known was 2O(k2 ) (log d)k−2...
Nitin Saxena, C. Seshadhri
WOWMOM
2009
ACM
146views Multimedia» more  WOWMOM 2009»
16 years 1 months ago
Optimization of WiMax modulation scheme with a cross layer erasure code
WIMAX (Worldwide Interoperability for Microwave Access) is a promising new networking technology that potentially offers high speed and wide area wireless access services that com...
Lei Zhang, Patrick Sénac, Roksana Boreli, M...
ICDE
2007
IEEE
120views Database» more  ICDE 2007»
16 years 29 days ago
Optimizing State-Intensive Non-Blocking Queries Using Run-time Adaptation
Main memory is a critical resource when processing non-blocking queries with state intensive operators that require real-time responses. While partitioned parallel processing can ...
Bin Liu, Mariana Jbantova, Elke A. Rundensteiner
IPCCC
2007
IEEE
16 years 28 days ago
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
Santosh Talli, Ram Srinivasan, Jeanine Cook