Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Abstract— Designing efficient algorithms for difficult multiobjective optimization problems is a very challenging problem. In this paper a new clustering multi-objective evolut...
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
We propose a new active learning algorithm to address the problem of selecting a limited subset of utterances for transcribing from a large amount of unlabeled utterances so that ...
Balakrishnan Varadarajan, Dong Yu, Li Deng, Alex A...
Abstract—Rateless coding ensures reliability by providing everincreasing redundancy, traditionally at the packet level (i.e. the application layer) through erasure coding. This p...