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FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
16 years 1 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
CEC
2009
IEEE
16 years 1 months ago
A clustering multi-objective evolutionary algorithm based on orthogonal and uniform design
Abstract— Designing efficient algorithms for difficult multiobjective optimization problems is a very challenging problem. In this paper a new clustering multi-objective evolut...
Yuping Wang, Chuangyin Dang, Hecheng Li, Lixia Han...
GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
ICASSP
2009
IEEE
16 years 1 months ago
Maximizing global entropy reduction for active learning in speech recognition
We propose a new active learning algorithm to address the problem of selecting a limited subset of utterances for transcribing from a large amount of unlabeled utterances so that ...
Balakrishnan Varadarajan, Dong Yu, Li Deng, Alex A...
ICC
2009
IEEE
166views Communications» more  ICC 2009»
16 years 1 months ago
A Cross-Layer Perspective on Rateless Coding for Wireless Channels
Abstract—Rateless coding ensures reliability by providing everincreasing redundancy, traditionally at the packet level (i.e. the application layer) through erasure coding. This p...
Thomas A. Courtade, Richard D. Wesel