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DAC
2009
ACM
16 years 7 months ago
Spare-cell-aware multilevel analytical placement
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yu...
DAC
1999
ACM
16 years 7 months ago
Power Efficient Mediaprocessors: Design Space Exploration
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
Johnson Kin, Chunho Lee, William H. Mangione-Smith...
DAC
2004
ACM
16 years 7 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
DAC
2005
ACM
16 years 7 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
MICCAI
2007
Springer
16 years 7 months ago
Detection of Spatial Activation Patterns as Unsupervised Segmentation of fMRI Data
In functional connectivity analysis, networks of interest are defined based on correlation with the mean time course of a user-selected `seed' region. In this work we propose ...
Polina Golland, Yulia Golland, Rafael Malach