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SAMOS
2004
Springer
15 years 12 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
CGO
2003
IEEE
15 years 12 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
TPCG
2003
IEEE
15 years 11 months ago
Guided Navigation in Task-Oriented 3D Graph Visualizations
In many application areas an optimal visualization of a complex graph depends on the specific task to be accomplished by the user. Therefore a means of locally customizable layou...
Guido Reina, Sven Lange-Last, Klaus D. Engel, Thom...
CODES
2002
IEEE
15 years 11 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
CLUSTER
2000
IEEE
15 years 11 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada