2652 search results - page 177 / 531 » Optimal design in collaborative design network |
166
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
183
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FPGA
2009
ACM
16 years 1 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
192
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MICRO
2006
IEEE
16 years 16 days ago
2006
IEEE
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
167
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CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
202
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IPSN
2010
Springer
16 years 1 months ago
2010
Springer
Shared sensing infrastructures that allow multiple applications to share deployed sensors are emerging and Internet protocol based access for such sensors has already been prototy...