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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
16 years 9 days ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 10 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ETS
2009
IEEE
117views Hardware» more  ETS 2009»
15 years 4 months ago
A Two Phase Approach for Minimal Diagnostic Test Set Generation
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
GECCO
2009
Springer
128views Optimization» more  GECCO 2009»
15 years 11 months ago
Evolving stochastic processes using feature tests and genetic programming
The synthesis of stochastic processes using genetic programming is investigated. Stochastic process behaviours take the form of time series data, in which quantities of interest v...
Brian J. Ross, Janine H. Imada
ECRTS
2003
IEEE
15 years 12 months ago
An Improved Schedulability Test for Uniprocessor Periodic Task Systems
We present a sufficient linear-time schedulability test for preemptable, asynchronous, periodic task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an ...
UmaMaheswari C. Devi