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VTS
2003
IEEE
115views Hardware» more  VTS 2003»
15 years 11 months ago
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Kr...
WCRE
2003
IEEE
15 years 11 months ago
GUI Ripping: Reverse Engineering of Graphical User Interfaces for Testing
Graphical user interfaces (GUIs) are important parts of today’s software and their correct execution is required to ensure the correctness of the overall software. A popular tec...
Atif M. Memon, Ishan Banerjee, Adithya Nagarajan
CBSE
2011
Springer
14 years 6 months ago
Towards incremental component compatibility testing
Software components are increasingly assembled from other components. Each component may further depend on others, and each may have multiple active versions. The total number of ...
Il-Chul Yoon, Alan Sussman, Atif M. Memon, Adam A....
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
16 years 7 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
KBSE
2010
IEEE
15 years 5 months ago
Test generation to expose changes in evolving programs
Software constantly undergoes changes throughout its life cycle, and thereby it evolves. As changes are introduced into a code base, we need to make sure that the effect of the ch...
Dawei Qi, Abhik Roychoudhury, Zhenkai Liang