Sciweavers

3333 search results - page 618 / 667
» Optimal Power-Down Strategies
Sort
View
CODES
2005
IEEE
15 years 11 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
ICPADS
2005
IEEE
15 years 11 months ago
I/O Processor Allocation for Mesh Cluster Computers
As cluster systems become increasingly popular, more and more parallel applications require need not only computing power but also significant I/O performance. However, the I/O s...
Pangfeng Liu, Chun-Chen Hsu, Jan-Jan Wu
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
15 years 11 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
PLDI
2005
ACM
15 years 11 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
VEE
2005
ACM
199views Virtualization» more  VEE 2005»
15 years 11 months ago
Escape analysis in the context of dynamic compilation and deoptimization
In object-oriented programming languages, an object is said to escape the method or thread in which it was created if it can also be accessed by other methods or threads. Knowing ...
Thomas Kotzmann, Hanspeter Mössenböck