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ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
16 years 1 days ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh
INFOCOM
2003
IEEE
16 years 1 days ago
Time-Optimal Network Queue Control: The Case of a Single Congested Node
-We solve the problem of time-optimal network queue control: what are the input data rates that make network queue sizes converge to their ideal size in the least possible time aft...
Mahadevan Iyer, Wei Kang Tsai
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
15 years 11 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk
ICCAD
1996
IEEE
74views Hardware» more  ICCAD 1996»
15 years 11 months ago
Optimal non-uniform wire-sizing under the Elmore delay model
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area...
Chung-Ping Chen, Hai Zhou, D. F. Wong
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen