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PATMOS
2005
Springer
16 years 2 days ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
ICNP
2000
IEEE
15 years 11 months ago
A Topology-Independent Fair Queueing Model in Ad Hoc Wireless Networks
Fair queueing of rate and delay-sensitive packet flows in a shared-medium, multihop wireless network remains largely unaddressed because of the unique design issues such as locat...
Haiyun Luo, Songwu Lu
ICSE
1993
IEEE-ACM
15 years 10 months ago
Formal Approaches to Software Architecture
Over the past 15 years there has been increasing recognition that careful attention to the design of a system’s software architecture is critical to satisfying its requirements ...
David Garlan
ECBS
2006
IEEE
153views Hardware» more  ECBS 2006»
15 years 10 months ago
A Unified Approach for Verification and Validation of Systems and Software Engineering Models
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
Luay Alawneh, Mourad Debbabi, Yosr Jarraya, Andrei...
ACSW
2007
15 years 8 months ago
A Data Warehouse Architecture for Clinical Data Warehousing
Data warehousing methodologies share a common set of tasks, including business requirements analysis, data design, architectural design, implementation and deployment. Clinical da...
Tony R. Sahama, Peter R. Croll