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» Ontologies and Description Logics
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ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
15 years 10 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
KBSE
1999
IEEE
15 years 10 months ago
AML: An Architecture Meta-Language
The language AML is used to specify the semantics of architecture description languages, ADLs. It is a very primitive language, having declarations for only three constructs: elem...
David S. Wile
TABLEAUX
2000
Springer
15 years 10 months ago
Benchmark Analysis with FaCT
FaCT (Fast Classification of Terminologies) is a Description Logic (DL) classifier that can also be used for modal logic satisfiability testing. The FaCT system includes two reason...
Ian Horrocks
ICCAD
1997
IEEE
99views Hardware» more  ICCAD 1997»
15 years 10 months ago
High-level area and power estimation for VLSI circuits
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
Mahadevamurty Nemani, Farid N. Najm
DLOG
2003
15 years 7 months ago
Implementing Matching in ALE--First Results
Matching problems in Description Logics are theoretically well understood, with a variety of algorithms available for different DLs. Nevertheless, still no implementation of a ge...
Sebastian Brandt