191 search results - page 21 / 39 » On-Chip Communication Architecture for OC-768 Network Proces... |
167
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
136
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IEEEPACT
2008
IEEE
16 years 12 days ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
159
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IPPS
2006
IEEE
16 years 15 hour ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
143
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JCP
2006
15 years 6 months ago
2006
Recently, mobile agents have been proposed for efficient data dissemination in sensor networks. In the traditional client/server-based computing architecture, data at multiple sour...
146
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CLUSTER
2008
IEEE
16 years 14 days ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...