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DATE
2010
IEEE
162views Hardware» more  DATE 2010»
15 years 12 months ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
ISCA
2010
IEEE
314views Hardware» more  ISCA 2010»
15 years 12 months ago
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Power consumption has become a major constraint in the design of processors today. To optimize a processor for energyefficiency requires an examination of energy-performance trade...
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay...
3DPVT
2002
IEEE
219views Visualization» more  3DPVT 2002»
15 years 11 months ago
A Multi-Resolution Scheme ICP Algorithm for Fast Shape Registration
The iterative closest point (ICP) algorithm is widely used for the registration of geometric data. One of its main drawbacks is its quadratic time complexity O(N2 ) with the shape...
Timothée Jost, Heinz Hügli
CBMS
2002
IEEE
15 years 11 months ago
Content-Based and Metadata Retrieval in Medical Image Database
The need for systems that can stock, represent, and provide efficient retrieval facilities of images of particular interest is becoming very high in medicine. In this respect, a l...
Solomon Atnafu, Richard Chbeir, Lionel Brunie
CCGRID
2002
IEEE
15 years 11 months ago
Using TOP-C and AMPIC to Port Large Parallel Applications to the Computational Grid
Porting large applications to distributed computing platforms is a challenging task from a software engineering perspective. The Computational Grid has gained tremendous popularit...
Gene Cooperman, Henri Casanova, Jim Hayes, Thomas ...