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IPPS
2005
IEEE
16 years 12 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
ISCA
2005
IEEE
118views Hardware» more  ISCA 2005»
16 years 12 days ago
Continuous Optimization
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steve...
169
Voted
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
16 years 12 days ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
ISCC
2005
IEEE
105views Communications» more  ISCC 2005»
16 years 12 days ago
The Bandwidth Exchange Architecture
New applications for the Internet such as video on demand, grid computing etc. depend on the availability of high bandwidth connections with acceptable Quality of Service (QoS). T...
David Michael Turner, Vassilis Prevelakis, Angelos...
ISPASS
2005
IEEE
16 years 12 days ago
Simulation Differences Between Academia and Industry: A Branch Prediction Case Study
Computer architecture research in academia and industry is heavily reliant on simulation studies. While microprocessor companies have the resources to develop highly detailed simu...
Gabriel H. Loh
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