11348 search results - page 435 / 2270 » On time-scale designs for networks |
199
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
165
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INFOCOM
2009
IEEE
16 years 1 months ago
2009
IEEE
—This paper proposes a VIrtual Scanning Algorithm (VISA), tailored and optimized for road network surveillance. Our design uniquely leverages upon the facts that (i) the movement...
181
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
180
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ISLPED
2003
ACM
16 years 4 days ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
163
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...