11348 search results - page 209 / 2270 » On time-scale designs for networks |
205
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JSA
2010
15 years 1 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
162
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LCN
2007
IEEE
16 years 24 days ago
2007
IEEE
Abstract—In this paper we present the design and implementation of a small-scale marine sensor network. The network monitors the temperature in the Baltic Sea on different height...
207
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SASN
2006
ACM
16 years 14 days ago
2006
ACM
Mesh network is vulnerable to privacy attacks because of the open medium property of wireless channel, the fixed topology, and the limited network size. Traditional anonymous rou...
187
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NETWORKS
2010
15 years 5 months ago
2010
Maˇnuch and Stacho [7] introduced the problem of designing f-tolerant routings in optical networks, i.e., routings which still satisfy the given requests even if f failures occur...
188
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IPPS
1997
IEEE
15 years 10 months ago
1997
IEEE
In this paper we show the power of sampling techniques in designing efficient distributed algorithms. In particular, we show that using sampling techniques, on some networks, sele...