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» On the three-dimensional channel routing
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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 8 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
FPGA
2008
ACM
131views FPGA» more  FPGA 2008»
15 years 7 months ago
WireMap: FPGA technology mapping for improved routability
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishch...
JSS
2006
104views more  JSS 2006»
15 years 6 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
ICC
2009
IEEE
15 years 3 months ago
A Multicost Approach to Online Impairment-Aware RWA
Abstract--We design and implement a multicost impairmentaware routing and wavelength assignment algorithm for online traffic. In transparent optical networks the quality of a trans...
Kostas Christodoulopoulos, Konstantinos Manousakis...
CORR
2011
Springer
185views Education» more  CORR 2011»
14 years 9 months ago
Distributed SIR-Aware Scheduling in Large-Scale Wireless Networks
Opportunistic scheduling and routing can in principle greatly increase the throughput of decentralized wireless networks, but to be practical such algorithms must do so with small...
Chun-Hung Liu, Jeffrey G. Andrews