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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
16 years 1 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
HIPEAC
2005
Springer
16 years 9 days ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
CIAC
2000
Springer
210views Algorithms» more  CIAC 2000»
15 years 11 months ago
Computing a Diameter-Constrained Minimum Spanning Tree in Parallel
A minimum spanning tree (MST) with a small diameter is required in numerous practical situations. It is needed, for example, in distributed mutual exclusion algorithms in order to ...
Narsingh Deo, Ayman Abdalla
SIROCCO
2008
15 years 8 months ago
Remembering without Memory: Tree Exploration by Asynchronous Oblivious Robots
In the effort to understand the algorithmic limitations of computing by a swarm of robots, the research has focused on the minimal capabilities that allow a problem to be solved. ...
Paola Flocchini, David Ilcinkas, Andrzej Pelc, Nic...
CORR
2011
Springer
174views Education» more  CORR 2011»
15 years 1 months ago
Physical expander in Virtual Tree Overlay
Abstract. In this paper, we propose a new construction of constantdegree expanders motivated by their application in P2P overlay networks and in particular in the design of robust ...
Taisuke Izumi, Maria Potop-Butucaru, Mathieu Valer...