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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
16 years 5 days ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
WACV
2005
IEEE
16 years 5 days ago
A Model-Based Interactive Object Segmentation Procedure
A global parametric shape model (boundary) of the object is optimized according to evidence accumulated from local features and the prior probability of the model parameters learn...
Jie Zou
EGH
2005
Springer
16 years 4 days ago
Split-plane shadow volumes
We present a novel method for rendering shadow volumes. The core idea of the method is to locally choose between Z-pass and Z-fail algorithms on a per-tile basis. The choice is ma...
Samuli Laine
ESOP
2005
Springer
16 years 3 days ago
Interprocedural Herbrand Equalities
We present an aggressive interprocedural analysis for inferring value equalities which are independent of the concrete interpretation of the operator symbols. These equalities, cal...
Markus Müller-Olm, Helmut Seidl, Bernhard Ste...
GECCO
2005
Springer
117views Optimization» more  GECCO 2005»
16 years 3 days ago
Directional self-learning of genetic algorithm
In order to overcome the low convergence speed and prematurity of classical genetic algorithm, an improved method named directional self-learning of genetic algorithm (DSLGA) is p...
Lin Cong, Yuheng Sha, Licheng Jiao, Fang Liu