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RTCSA
2007
IEEE
16 years 20 days ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
16 years 20 days ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
GECCO
2007
Springer
183views Optimization» more  GECCO 2007»
16 years 16 days ago
Search-based testing of service level agreements
The diffusion of service oriented architectures introduces the need for novel testing approaches. On the one side, testing must be able to identify failures in the functionality ...
Massimiliano Di Penta, Gerardo Canfora, Gianpiero ...
VTC
2006
IEEE
16 years 11 days ago
Two-Level Fractional Guard Channels for Priority Access in Cellular Systems
– A two-level fractional guard channels (TLFGC) scheme to efficiently provide priority access for handoff calls over new calls in cellular systems is proposed. The switching betw...
David Tung Chong Wong, Jon W. Mark, Kee Chaing Chu...
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
16 years 7 hour ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...