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ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 11 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
ISCA
1993
IEEE
112views Hardware» more  ISCA 1993»
15 years 11 months ago
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors
The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with...
Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta
CVPR
2010
IEEE
15 years 11 months ago
Stratified Learning of Local Anatomical Context for Lung Nodules in CT Images
The automatic detection of lung nodules attached to other pulmonary structures is a useful yet challenging task in lung CAD systems. In this paper, we propose a stratified statist...
Dijia Wu, Le Lu, Jinbo Bi, Yoshihisa Shinagawa, Ki...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
15 years 11 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
STOC
2010
ACM
224views Algorithms» more  STOC 2010»
15 years 11 months ago
Satisfiability Allows No Nontrivial Sparsification Unless The Polynomial-Time Hierarchy Collapses
Consider the following two-player communication process to decide a language L: The first player holds the entire input x but is polynomially bounded; the second player is computa...
Holger Dell and Dieter van Melkebeek
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