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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
16 years 27 days ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
DEXAW
2006
IEEE
133views Database» more  DEXAW 2006»
16 years 27 days ago
A High-Level Architecture of a Metadata-based Ontology Matching Framework
One of the pre-requisites for the realization of the Semantic Web vision are matching techniques which are capable of handling the open, dynamic and heterogeneous nature of the se...
Malgorzata Mochol, Elena Paslaru Bontas Simperl
DSD
2006
IEEE
73views Hardware» more  DSD 2006»
16 years 27 days ago
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications
We propose a novel two-level Boolean minimizer coming in succession to our previously developed minimizer BOOM, so we have named it BOOM-II. It is a combination of two minimizers,...
Petr Fiser, Hana Kubatova
DSN
2006
IEEE
16 years 27 days ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August