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ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
16 years 1 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
16 years 1 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
IV
2007
IEEE
123views Visualization» more  IV 2007»
16 years 1 months ago
Visual Mining of Multi-Modal Social Networks at Different Abstraction Levels
Lisa Singh, Mitchell Beard, Lise Getoor, M. Brian ...
MEMOCODE
2007
IEEE
16 years 1 months ago
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
Orthogonal Frequency-Division Multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral...
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Da...
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
16 years 1 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...