Sciweavers

20511 search results - page 279 / 4103
» On the level
Sort
View
IPPS
2007
IEEE
16 years 1 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ISCAS
2007
IEEE
93views Hardware» more  ISCAS 2007»
16 years 1 months ago
Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform
Jung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol P...
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
16 years 1 months ago
Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients
—Discrete Cosine Transform (DCT) has been widely used in image/video coding systems, where zigzag scan is usually employed for DCT coefficient organization. However, due to local...
Li Zhang, Wen Gao, Qiang Wang, Debin Zhao
ISORC
2007
IEEE
16 years 1 months ago
System-Level Energy-Efficiency for Real-Time Tasks
Chuan-Yue Yang, Jian-Jia Chen, Chia-Mei Hung, Tei-...
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
16 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...