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DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
16 years 1 months ago
New Strategies for System-Level Design
Daniel D. Gajski
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
16 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
DSN
2007
IEEE
16 years 1 months ago
Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the fai...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
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DSN
2007
IEEE
16 years 1 months ago
Processor-Level Selective Replication
Full duplication of an entire application (through spatial or temporal redundancy) would detect many errors that are benign to the application from the perspective of the end-user...
Nithin Nakka, Karthik Pattabiraman, Ravishankar K....