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ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
16 years 3 months ago
Quality Improvement Methods for System-Level Stimuli Generation
Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce re...
Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
16 years 3 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
ICCD
2004
IEEE
79views Hardware» more  ICCD 2004»
16 years 3 months ago
Using Circuits and Systems-Level Research to Drive Nanotechnology
This paper details nano-scale devices being researched by physical scientists to build computational systems. It also reviews some existing system design work that uses the device...
Michael T. Niemier, Ramprasad Ravichandran, Peter ...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 3 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2004
IEEE
61views Hardware» more  ICCAD 2004»
16 years 3 months ago
Timing analysis considering spatial power/ground level variation
Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Ono...