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HPCA
2008
IEEE
16 years 7 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
HPCA
2007
IEEE
16 years 7 months ago
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
Stijn Eyerman, Lieven Eeckhout
HPCA
2006
IEEE
16 years 7 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
HPCA
2003
IEEE
16 years 7 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
CHI
2002
ACM
16 years 7 months ago
SmartSkip: consumer level browsing and skipping of digital video content
In this paper, we describe an interface for browsing and skipping digital video content in a consumer setting; that is, sitting and watching television from a couch using a standa...
Steven M. Drucker, Asta Glatzer, Steven De Mar, Cu...