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168
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SAMOS
2004
Springer
16 years 1 days ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
173
Voted
ISCA
2003
IEEE
120views Hardware» more  ISCA 2003»
15 years 12 months ago
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
Milos Prvulovic, Josep Torrellas
CLUSTER
2002
IEEE
15 years 11 months ago
High Performance User Level Sockets over Gigabit Ethernet
While a number of User-Level Protocols have been developed to reduce the gap between the performance capabilities of the physical network and the performance actually available, a...
Pavan Balaji, Piyush Shivam, Pete Wyckoff, Dhabale...
CLUSTER
2002
IEEE
15 years 11 months ago
User-Level Remote Data Access in Overlay Metacomputers
A practical problem faced by users of metacomputers and computational grids is: If my computation can move from one system to another, how can I ensure that my data will still be ...
Jeff Siegel, Paul Lu
183
Voted
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 11 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...