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IROS
2006
IEEE
159views Robotics» more  IROS 2006»
16 years 22 days ago
Multi-Level Surface Maps for Outdoor Terrain Mapping and Loop Closing
— To operate outdoors or on non-flat surfaces, mobile robots need appropriate data structures that provide a compact representation of the environment and at the same time suppo...
Rudolph Triebel, Patrick Pfaff, Wolfram Burgard
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
16 years 22 days ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
CODES
2005
IEEE
16 years 10 days ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
IPPS
2005
IEEE
16 years 9 days ago
Automatic Support for Irregular Computations in a High-Level Language
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
Jimmy Su, Katherine A. Yelick
171
Voted
MM
2005
ACM
157views Multimedia» more  MM 2005»
16 years 8 days ago
Chameleon: application level power management with performance isolation
In this paper, we present Chameleon—an application-level power management approach for reducing energy consumption in mobile processors. Our approach exports the entire responsi...
Xiaotao Liu, Prashant J. Shenoy, Mark D. Corner