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TC
2010
15 years 1 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
TCAD
2010
121views more  TCAD 2010»
15 years 1 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
TITB
2010
111views Education» more  TITB 2010»
15 years 1 months ago
ECG signal compression and classification algorithm with quad level vector for ECG holter system
An ECG signal processing method with quad level vector (QLV) is proposed for the ECG holter system. The ECG processing consists of the compression flow and the classification flow,...
Hyejung Kim, Refet Firat Yazicioglu, Patrick Merke...
TPDS
2010
125views more  TPDS 2010»
15 years 1 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
TR
2010
131views Hardware» more  TR 2010»
15 years 1 months ago
A Memetic Algorithm for Multi-Level Redundancy Allocation
Redundancy allocation problems (RAPs) have attracted much attention for the past thirty years due to its wide applications in improving the reliability of various engineering syste...
Zai Wang, Ke Tang, Xin Yao