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ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
15 years 10 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DAC
1996
ACM
15 years 10 months ago
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
Elisabeth Berrebi, Polen Kission, Serge Vernalde, ...
DAC
1996
ACM
15 years 10 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
IWANN
1997
Springer
15 years 10 months ago
Gray-Level Object Segmentation with a Network of FitzHugh-Nagumo Oscillators
Abstract. In this paper we adopt a temporal coding approach to neuronal modeling of the visual cortex, using oscillations. We propose a hierarchy of three processing modules corres...
Abderrahim Labbi, Ruggero Milanese, Holger Bosch
ISCA
1993
IEEE
113views Hardware» more  ISCA 1993»
15 years 10 months ago
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History
Recent attention to speculative execution as a mechanism for increasing performance of single instruction streams has demanded substantially better branch prediction than what has...
Tse-Yu Yeh, Yale N. Patt