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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
16 years 1 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
16 years 1 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
ICIP
2008
IEEE
16 years 1 months ago
A fast level set algorithm for shape-based segmentation with multiple selective priors
This paper addresses the shape-based segmentation problem using level sets. In particular, we propose a fast algorithm to solve the piece-wise constant Chan-Vese segmentation mode...
Rachid Fahmi, Aly A. Farag
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
16 years 1 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
DSN
2007
IEEE
16 years 29 days ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...