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DAC
2010
ACM
15 years 10 months ago
Theoretical analysis of gate level information flow tracking
Understanding the flow of information is an important aspect in computer security. There has been a recent move towards tracking information in hardware and understanding the flow...
Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Tim...
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
15 years 10 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 10 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DEXAW
2004
IEEE
124views Database» more  DEXAW 2004»
15 years 10 months ago
A Metadata Application Profile for Collection-Level Description of Digital Folklore Resources
The preservation and representation of folklore collections is a basic priority for every country because they are valuable for studying the customs and the tradition of specific ...
Irene Lourdi, Christos Papatheodorou
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 10 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...