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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
16 years 6 days ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
DSN
2005
IEEE
16 years 6 days ago
A Framework for Node-Level Fault Tolerance in Distributed Real-Time Systems
This paper describes a framework for achieving node-level fault tolerance (NLFT) in distributed realtime systems. The objective of NLFT is to mask errors at the node level in orde...
Joakim Aidemark, Peter Folkesson, Johan Karlsson
FPT
2005
IEEE
198views Hardware» more  FPT 2005»
16 years 6 days ago
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
Wolfgang Klingauf, Robert Günzel
ICMCS
2005
IEEE
132views Multimedia» more  ICMCS 2005»
16 years 5 days ago
A Two-Level CBIR Platform with Application to Brain MRI Retrieval
This paper presents a novel platform for image retrieval based on a two-level architecture inspired from human cognitive mechanisms. These two levels provide both generic similari...
John Moustakas, Kostas Marias, Socrates Dimitriadi...
SBCCI
2005
ACM
136views VLSI» more  SBCCI 2005»
16 years 4 days ago
Current mask generation: a transistor level security against DPA attacks
The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or elect...
Daniel Mesquita, Jean-Denis Techer, Lionel Torres,...