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DATE
2002
IEEE
99views Hardware» more  DATE 2002»
15 years 11 months ago
Gate Level Fault Diagnosis in Scan-Based BIST
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
Ismet Bayraktaroglu, Alex Orailoglu
DATE
2002
IEEE
122views Hardware» more  DATE 2002»
15 years 11 months ago
Exploiting Idle Cycles for Algorithm Level Re-Computing
Although algorithm level re-computing techniques can trade-off the detection capability of Concurrent Error Detection (CED) vs. time overhead, it results in 100% time overhead whe...
Kaijie Wu, Ramesh Karri
ECRTS
2002
IEEE
15 years 11 months ago
Managing Multi-Mode Tasks with Time Cost and Quality Levels using Optimal Discrete Control Synthesis
Real-time control systems are complex to design, and automation support is important. We are interested in systems with multiple tasks, each with multiple modes, implementing a fu...
Hervé Marchand, Éric Rutten
ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
15 years 11 months ago
Transient sensitivity computation for transistor level analysis and tuning
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Tuyen V. Nguyen, Peter O'Brien, David W. Winston
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
15 years 10 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...