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DAC
2005
ACM
16 years 7 months ago
Simulation based deadlock analysis for system level designs
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...
MICCAI
2003
Springer
16 years 7 months ago
Interactive, GPU-Based Level Sets for 3D Segmentation
While level sets have demonstrated a great potential for 3D medical image segmentation, their usefulness has been limited by two problems. First, 3D level sets are relatively slow ...
Aaron E. Lefohn, Joshua E. Cates, Ross T. Whitaker
ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
16 years 3 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
IEEEARES
2010
IEEE
16 years 1 months ago
Secure Monitoring of Service Level Agreements
—Service Level Agreements (SLA) are commonly used to define terms and conditions of service provisioning. WS-Agreement1 is an SLA specification that addresses the need of both ...
K. P. Clark, Martijn Warnier, Frances M. T. Brazie...
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
16 years 29 days ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...