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CONCUR
1997
Springer
15 years 11 months ago
Modularity for Timed and Hybrid Systems
Abstract. In a trace-based world, the modular speci cation, veri cation, and control of live systems require each module to be receptive that is, each module must be able to meet i...
Rajeev Alur, Thomas A. Henzinger
ICPP
1996
IEEE
15 years 11 months ago
Polynomial-Time Nested Loop Fusion with Full Parallelism
Data locality and synchronization overhead are two important factors that affect the performance of applications on multiprocessors. Loop fusion is an effective way for reducing s...
Edwin Hsing-Mean Sha, Chenhua Lang, Nelson L. Pass...
FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
15 years 11 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
FOCS
1993
IEEE
15 years 11 months ago
Scale-sensitive Dimensions, Uniform Convergence, and Learnability
Learnability in Valiant’s PAC learning model has been shown to be strongly related to the existence of uniform laws of large numbers. These laws define a distribution-free conver...
Noga Alon, Shai Ben-David, Nicolò Cesa-Bian...
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
15 years 11 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
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