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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
GLOBECOM
2007
IEEE
16 years 1 months ago
Uncertainty Mitigation for Utility-Oriented Routing in Wireless Ad Hoc Networks
— Link and node reliability are important metrics in wireless ad hoc networks. Therefore, evaluating and quantifying reliability has become the cornerstone of research in this ď¬...
Feng Li, Avinash Srinivasan, Mingming Lu, Jie Wu
HPDC
2007
IEEE
16 years 1 months ago
Precise and realistic utility functions for user-centric performance analysis of schedulers
Utility functions can be used to represent the value users attach to job completion as a function of turnaround time. Most previous scheduling research used simple synthetic repre...
Cynthia Bailey Lee, Allan Snavely
ICC
2007
IEEE
16 years 1 months ago
Modulation Schemes Based on Orthogonal Pulses for Time Hopping Ultra Wideband Radio Systems
— This paper describes a combined modulation scheme for time hopping ultra wideband (TH-UWB) radio systems using on-off keying (OOK) and pulse shape modulation (PSM). For this sc...
Sudhan Majhi, A. S. Madhukumar, A. Benjamin Premku...
ICCAD
2007
IEEE
105views Hardware» more  ICCAD 2007»
16 years 1 months ago
Victim alignment in crosstalk aware timing analysis
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
Ravikishore Gandikota, Kaviraj Chopra, David Blaau...
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