415 search results - page 23 / 83 » On the energy-efficiency of speculative hardware |
150
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MICRO
1998
IEEE
15 years 10 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
164
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IPPS
2007
IEEE
16 years 11 days ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
160
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
149
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MICRO
1993
IEEE
15 years 10 months ago
1993
IEEE
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelism ILP found in non-numeric programs. An importantpr...
148
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ISCA
1995
IEEE
15 years 9 months ago
1995
IEEE
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...