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CODES
2004
IEEE
15 years 10 months ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
IPPS
1999
IEEE
15 years 11 months ago
Design and Implementation of a Scalable Parallel System for Multidimensional Analysis and OLAP
Multidimensional Analysis and On-Line Analytical Processing (OLAP) uses summary information that requires aggregate operations along one or more dimensions of numerical data value...
Sanjay Goil, Alok N. Choudhary
IJCAT
2010
106views more  IJCAT 2010»
15 years 5 months ago
Fine grain associative feature reasoning in collaborative engineering
: This paper explores the vast domain of systematic collaborative engineering with reference to product lifecycle management approach from the angle of feature-level collaboration ...
Yong-Sheng Ma, C. H. Bong
DAC
2006
ACM
16 years 7 months ago
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. ali...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
183
Voted
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
16 years 7 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture