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ISQED
2009
IEEE
91views Hardware» more  ISQED 2009»
16 years 1 months ago
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ISCA
2005
IEEE
79views Hardware» more  ISCA 2005»
16 years 8 days ago
Design and Evaluation of Hybrid Fault-Detection Systems
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
JSA
2010
158views more  JSA 2010»
15 years 1 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
MSWIM
2009
ACM
16 years 1 months ago
Design and evaluation of host identity protocol (HIP) simulation framework for INET/OMNeT++
Host Identity Protocol (HIP) decouples IP addresses from higher layer Internet applications by proposing a new, cryptographic namespace for host identities. HIP has great potentia...
László Bokor, Szabolcs Novácz...
IPPS
2008
IEEE
16 years 1 months ago
The design of a versatile, secure P2PSIP communications architecture for the public internet
Communications systems, encompassing VoIP, IM, and other personal media, present different challenges for P2P environments than other P2P applications. In particular, reliable com...
David A. Bryan, Bruce Lowekamp, Marcia Zangrilli