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ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
16 years 3 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
16 years 3 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
ISQED
2010
IEEE
114views Hardware» more  ISQED 2010»
16 years 1 months ago
Toward effective utilization of timing exceptions in design optimization
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
LCTRTS
2010
Springer
16 years 1 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
SASO
2009
IEEE
16 years 1 months ago
Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
We investigate a generic self-adaptation method to reduce the design effort for System-on-Chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have b...
Andreas Bernauer, Oliver Bringmann, Wolfgang Rosen...
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