Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
Object-oriented programs are notable for making use of both rder abstractions and mutable, aliased state. Either feature alone is challenging for formal verification, and the com...
Neelakantan R. Krishnaswami, Jonathan Aldrich, Lar...