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PRDC
2007
IEEE
16 years 12 days ago
Power-Performance Trade-Off of a Dependable Multicore Processor
As deep submicron technologies are advanced, new challenges, such as power consumption and soft errors, are emerging. A naïve technique, which utilizes emerging multicore process...
Toshinori Sato, Toshimasa Funaki
APCCAS
2006
IEEE
229views Hardware» more  APCCAS 2006»
16 years 6 days ago
Low Power Combinational Multipliers using Data-driven Signal Gating
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
Nima Honarmand, Ali Afzali-Kusha
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
16 years 6 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
ISCAS
2007
IEEE
136views Hardware» more  ISCAS 2007»
16 years 12 days ago
Flexible Low Power Probability Density Estimation Unit For Speech Recognition
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
Ullas Pazhayaveetil, Dhruba Chandra, Paul Franzon
DAC
2004
ACM
15 years 11 months ago
A new state assignment technique for testing and low power
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....