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CORR
2010
Springer
89views Education» more  CORR 2010»
15 years 6 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
CORR
2010
Springer
81views Education» more  CORR 2010»
15 years 6 months ago
Understanding Cascading Failures in Power Grids
In the past, we have observed several large blackouts, i.e. loss of power to large areas. It has been noted by several researchers that these large blackouts are a result of a cas...
Sachin Kadloor, Nandakishore Santhi
TWC
2008
129views more  TWC 2008»
15 years 6 months ago
Spatial Multiplexing Architectures with Jointly Designed Rate-Tailoring and Ordered BLAST Decoding - Part II: A Practical Method
The study of the class of new spatial multiplexing architectures (SMAs) is continued. As introduced in Part I of this paper, the SMAs consist of joint design of rate and power all...
Yi Jiang, Mahesh K. Varanasi
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 10 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
15 years 10 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...