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CF
2007
ACM
15 years 10 months ago
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols
In this work we reduce interconnect power dissipation in Symmetric Multiprocessors or SMPs. We revisit snoopy cache coherence protocols and reduce unnecessary interconnect activit...
Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
IBMRD
2006
76views more  IBMRD 2006»
15 years 6 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain
WIOPT
2010
IEEE
15 years 4 months ago
Optimizing power allocation in interference channels using D.C. programming
Abstract--Power allocation is a promising approach for optimizing the performance of mobile radio systems in interference channels. In the present paper, the non-convex objective f...
Hussein Al-Shatri, Tobias Weber
VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
15 years 11 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
15 years 11 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh