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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
16 years 3 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
16 years 3 months ago
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
Zhuo Feng, Peng Li
TCC
2010
Springer
324views Cryptology» more  TCC 2010»
16 years 3 months ago
Leakage-Resilient Signatures
The strongest standard security notion for digital signature schemes is unforgeability under chosen message attacks. In practice, however, this notion can be insufficient due to â€...
Sebastian Faust, Eike Kiltz, Krzysztof Pietrzak, G...
CVPR
2010
IEEE
16 years 3 months ago
Curious Snakes: a minimum-latency solution to the cluttered background problem in active contours
We present a region-based active contour detection algorithm for objects that exhibit relatively homogeneous photometric characteristics (e.g. smooth color or gray levels), embe...
Ganesh Sundaramoorthi, Stefano Soatto, Anthony Yez...
ISPASS
2010
IEEE
16 years 1 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
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