2173 search results - page 234 / 435 » On the Values of Reducibility Candidates |
151
click to vote
ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
187
click to vote
ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
151
click to vote
ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
172
click to vote
ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
139
click to vote
ARITH
2009
IEEE
16 years 1 months ago
2009
IEEE
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand v...