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ET
2002
90views more  ET 2002»
15 years 6 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ICIP
2010
IEEE
15 years 4 months ago
Geometric averaging of X-ray signals in automatic exposure control
Improper dose control in X-ray cardio-vascular systems leads to a reduced Signal-to-Noise Ratio (SNR) in regions of interest of the X-ray image. We aim at reducing the influence o...
Rudolph M. Snoeren, Peter H. N. de With
ICASSP
2011
IEEE
14 years 10 months ago
Accurate parameter generation using fixed-point arithmetic for embedded HMM-based speech synthesizers
Parameter trajectory generation for HMM-based speech synthesis is practically achieved using only fixed-point arithmetic with 32-bit integers. Since processors for embedded devic...
Nobuyuki Nishizawa, Tsuneo Kato
HPCA
2009
IEEE
16 years 7 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
KDD
2006
ACM
156views Data Mining» more  KDD 2006»
16 years 7 months ago
Discovering significant OPSM subspace clusters in massive gene expression data
Order-preserving submatrixes (OPSMs) have been accepted as a biologically meaningful subspace cluster model, capturing the general tendency of gene expressions across a subset of ...
Byron J. Gao, Obi L. Griffith, Martin Ester, Steve...