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» On the Use of Formal Techniques for Validation
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IFM
2004
Springer
15 years 12 months ago
Verifying Controlled Components
Recent work on combining CSP and B has provided ways of describing systems comprised of components described in both B (to express requirements on state) and CSP (to express intera...
Steve Schneider, Helen Treharne
DAC
2007
ACM
16 years 7 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
SIGSOFT
2008
ACM
16 years 7 months ago
Towards compositional synthesis of evolving systems
Synthesis of system configurations from a given set of features is an important and very challenging problem. This paper makes a step towards this goal by describing an efficient ...
Shiva Nejati, Mehrdad Sabetzadeh, Marsha Chechik, ...
RWEB
2009
Springer
16 years 1 months ago
Description Logics
In this chapter we will introduce description logics, a family of logic-based knowledge representation languages that can be used to represent the terminological knowledge of an a...
Franz Baader
TABLEAUX
2007
Springer
16 years 21 days ago
Bounded Model Checking with Description Logic Reasoning
Abstract. Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the sys...
Shoham Ben-David, Richard J. Trefler, Grant E. Wed...